1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory containing a cascade dynamic memory cell array capable of storing bits of information on a bit basis.
2. Description of the Related Art
DRAM cells now in practical use are composed of a transfer gate MOS (insulated-gate type) transistor connected to a word line and a bit line, and an information storing capacitor connected to this transistor.
The inventor of this application has proposed a cascade gate semiconductor memory cell with a view to squeezing more DRAM cells in a single chip at lower per-bit cost, as disclosed in U.S. patent application Ser. No. 687,687.
The cascade gate memory cell is capable of storing bits of information on a bit basis. An array of memory cells of this type requires the memory cells to connect to the bit lines at a rate of one connection for every plurality of bits. This allows much higher packing density than a DRAM using a conventional single-transistor, single-capacitor cell array, thereby reducing the per-bit cost remarkably.
The inventor has also proposed a semiconductor memory device that comprises the above cascade gate memory cell array and a storing means for temporarily storing bits of information read time-sequentially from a memory cell, and that can rewrite (or write) the bits of information after the reading is complete, as disclosed in U.S. patent application Ser. No. 721,255.
In the above cascade memory cell, although the smaller per-bit capacitor size tends to lower its capacitance Cs, only connection of memory cells with bit lines for every plurality of bits reduces the bit-line capacitance Cb. With an increasing capacity of cell arrays, however, an attempt to increase the number of bits per bit line will make the value Cb/Cs larger, introducing the risk of the sense margin of the bit-line sense amplifier being reduced in the read operation.